1.6Tb class modules are actually being developed to satisfy the uncooked bandwidth and bandwidth density calls for of purposes together with ‘manufacturing facility scale’ AI and hyperscale computing. Based mostly on rising requirements from IEEE and OIF, they construct upon a strong 800Gb ecosystem and embody a number of new options – each evolutionary and revolutionary.
224G Signaling and FECi
The obvious change is the transfer to 224G signaling. At 1.6Tb, we are going to see two new speeds: eight lanes of 212.5Gb/s for the host-to-module interface and 226.875Gb/s for some optical interfaces. The sooner 226.875Gb charge introduces a revolutionary facet for shopper optics: an internal FEC, generally known as FECi.
The host interface based mostly on 212.5Gb already makes use of the well-established RS FEC for error safety. This FECo, an outer FEC, is used on all interfaces, whereas sure optical PMDs require greater coding acquire offered by the extra FECi. What provides to the revolutionary facet of the FECi is the usage of a soft-decision Hamming (128,120) code. The usage of the soft-decision FEC means shut coupling of the PAM-4 RX PHY and the FECi decode logic to realize most coding acquire. Whereas this soft-decision method might have a small energy burden, the coding acquire influence for interfaces is significant.
This FECi performance is applied contained in the optical module as a result of it’s PMD dependent, which drives new complexity for module improvement, testing and validation. Along with the event and testing of the brand new advanced FECi purposeful logic, there’s extra module F/W wanted to help this, particularly for reporting FEC RX parameters.
Image Mux Over Traditional Bit Mux
One other change is the transfer to image mux over the basic bit mux used at 800Gb and under. This method will assist extract extra advantages in error discount.
VIAVI has been the reference for each shopper and digital coherent module improvement, testing and validation for the reason that early days of 100G. We’ve all the time taken an built-in method, together with PHY, photonics and firmware.
This built-in method is extra important than ever. Our expertise with FEC logic stress and validation will now play a task as FECi logic and efficiency should be validated on the module degree. Subsequently, we should undertake a four-pronged method for module improvement, debugging and validation.
The 4-Pronged Method for Module Growth, Debugging and Validation
- Photonic Layer: the VIAVI MAP product line can handle and stress the photonic interconnect to make sure repeatable and recognized optical alerts arrive on the module.
- PHY Layer: Bit errors, bursts and bit slips should all be categorized and analyzed. Stressing in clock PPM and section is important to validate CDR and DLL efficiency and stability.
- Firmware: CMIS is an integral a part of the host and the module. Modifications on the photonic and PHY layers should be precisely mirrored within the module firmware.
- Logic: The FECi logic integrates photonic and firmware reporting elements. Primarily it represents a big block of advanced logic that should be validated for logical efficiency and energy integrity.
VIAVI Can Assist!
To be taught extra about our complete and built-in method to module take a look at and validation – go to VIAVISolutions.com or converse to our VIAVI purposes staff.
Learn our different latest blogs: Bamboozled by Bit Errors?, When ‘Simply Good Sufficient’ isn’t Good Sufficient, Built-in Testing Simplifies DCO Complexities, What’s All This Error Fingerprint Stuff?, and Lab and stay Ethernet testing at scale – 800G and past
